Comments for SPISim: EDA for Signal Integrity, Power Integrity and Circuit Simulation

Comment on IBIS Model: Model parameters and Spec. by Porsche Starrs

Porsche Starrs — Wed, 24 Jul 2019 11:41:04 +0000

Hello there! It’s hard to find anything interesting in this particular subject (I mean something that is not overly simplistic), because everything related to 3D seems rather difficult. You however seem like you know what you’re talking about 🙂 Thank you for finding time to write relevant content for us!

Comment on S-Param: Quality checklist by S-Param indicators: ILFitatNq, ILD, ICN, ICR, IMR, INEXT, PQM, CQM... | SPISim: EDA for Signal Integrity, Power Integrity and Circuit Simulation

Wed, 08 May 2019 20:21:21 +0000

[…] we have written a post [LINKED HERE] detailing how these metrics are calculated. Interested readers may also wait for upcoming P370 spec. […]

Comment on A quick and easy IBIS modeling flow by IBIS-AMI: An end-to-end AMI modeling flow | SPISim: EDA for Signal Integrity, Power Integrity and Circuit Simulation

Mon, 17 Dec 2018 23:45:14 +0000

[…] ← Previous […]

Comment on Differential modeling flow: Development by 簡單快速的IBIS建模流程 | SPISim[使必信科技]: 信號完整性、電源完整性暨電路擬真軟體

簡單快速的IBIS建模流程 | SPISim[使必信科技]: 信號完整性、電源完整性暨電路擬真軟體 — Mon, 17 Dec 2018 00:54:24 +0000

[…] 第二道的關卡在於VT的仿真部份, 由上述的曲面建構出series model 之後, 我們要能在VT瞬態仿真時將其消除才能不被算了兩次 (double count); 對於一個spice 仿真器而言, 大部份的情況其都不允許負電阻、負電容等的存在, 也就是說, 它們會把這些負值元件看做是用戶的輸入錯誤而不讓仿真繼續進行, 解決之道, 吾人可以用如本司在2016年Asian IBIS Summit所展演的Verilog-A 電路或是仿真器大都會提供的控制電源來達成這種”負電阻”似的消去目的;即便是如此, 在Verilog-A的解決方案上, look-up table上每個grid的大小係由iv二維描描所決定, 而控制電源的解決方案上, 為了要能算出適當的控制電源參數, 建模者還得利用最佳化的原理才能算出何種組合的參數最能描述上一步算出的反應曲面; 而這些不論是表格或是參數變化間的圓滑性(smoothness), 也都更進一步地決定了仿真的收斂性。凡此種種情況,難怪cook-book裡描述此段的部份(見下圖描述的前兩行)作者只是輕輕一語帶過而不做詳述, 因為真的是說得比做得還簡單啊。 […]

Comment on IBIS model: How does IBIS work by A quick an easy IBIS modeling flow | SPISim: EDA for Signal Integrity, Power Integrity and Circuit Simulation

Thu, 13 Dec 2018 22:56:33 +0000

[…] In previous post, we explained how IBIS model’s data are used in a circuit simulation. Simply speaking, the “VT” data is considered as “target” while “IV” data are used to compute “switching coefficients” so that appropriate amount of current will be injected or withdrawn from the buffer to achieve the nodal voltage specified by that VT table at that particular time point. Because there are switching coefficients for both pull-up and pull-down structures… need two equations to solve for two unknowns, thus two set of VT, each under different test loads, are required. Based on this algorithm, an IV data and calculated coefficients are actually “paired” and affect each other. If current in IV table is larger, than the calculated coefficients will become smaller so that overall injected/withdrawn current will still be the same. In this sense, the actual IV data is not that important as it will always be “adjusted” or weighted by the parameters. […]

Comment on Differential modeling flow: Development by A quick an easy IBIS modeling flow | SPISim: EDA for Signal Integrity, Power Integrity and Circuit Simulation

Thu, 13 Dec 2018 21:08:08 +0000

[…] and not many are for the traditional IBIS part… except for our Verilog-A based approach presented at the 2016 Asian summit. In this post, I would like to first review these “formal” process, dive into how each […]

Comment on Simulate IBIS Data with Free Spice [Part 1] by admin@SPISim

admin@SPISim — Thu, 20 Sep 2018 17:20:34 +0000

There are waveform sections in an ibis model, i.e. [Rising Waveform] and [Falling Waveform]. The 20%~80% transition value of these waveform are defined as RTR and RTF. You may also find IBIS spec. for more information about how these can be calculated. The calculated parameters are stored with “RAMP” keywords in an ibis model.

Comment on Simulate IBIS Data with Free Spice [Part 1] by James Johnson

James Johnson — Mon, 13 Aug 2018 22:46:04 +0000

How are the ramp control values RISERMP (RTR) and FALLRMP (RTF) derived from the dV/dt values found in the IBIS files?

Comment on S-Param: Quality checklist by SERDES 通道分析三部曲 | SPISim[使必信科技]: 信號完整性、電源完整性暨電路擬真軟體

SERDES 通道分析三部曲 | SPISim[使必信科技]: 信號完整性、電源完整性暨電路擬真軟體 — Sun, 08 Apr 2018 18:57:44 +0000

[…] 通道分析第一步的是對通道做時域仿真以得到其響應,如前所說我們也把TX/RX的類比前端包括在仿真的原理圖或網表裡,並以全部響應會是LTI為假設。如果現有欲分析的通路是佈線後的結果,則第三方的全波場解程式則為必需, 因為諸如VIA或連接器等都需以全波的形式場解(field solve)才能得到精確的描述;broadband spice也常是需要的, 因其可將場解出的頻域轉成如RLC/EFGH的仿真器內建元件而於時域上使用;若通道是為佈線前的分析, 則這些Via/Connector的模型仍為必需但傳輸線的部份則可以現有元件代替。如果S參數會一同參與仿真的話則這裡沒做更多說明的部份、即藏在魔鬼裡的細節、包括了調適S參數以期為passive, causal, symmetric and asympotic 以及最終將單端的S參數轉成差分的形式。當所有的模型都就緒之後, 則可到我們的[SPISim_IBIS 程式]端並把IBIS 轉成免費仿真器可支援的格式: […]

Comment on Blog Articles Index by A channel analysis trilogy | SPISim: EDA for Signal Integrity, Power Integrity and Circuit Simulation

Sun, 08 Apr 2018 17:31:24 +0000

[…] Blog Articles Index […]